Various issues arise in attempting to satisfy the ever increasing demands for miniaturization, particularly in fabricating non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. The demands for continuing miniaturization have led to the fabrication of flash memory devices comprising transistors having a gate width of about 0.13 micron and under a gap between gate structures spaced apart by about 0.33 micron or less. In accordance with conventional practices, an oxide sidewall spacer is formed on side surfaces of the gate stack and a conformal silicon nitride layer, serving as an etch stop layer, is deposited over the gate structures including the sidewall spacers, thereby further reducing the gap between gate structures to about 0.15 micron or less. In accordance with conventional practices, a first interlayer dielectric (ILD0) is deposited over the gate structures and fills the gaps therebetween. Such an oxide layer is typically a boron-phosphorus-doped silicate glass (BPSG), typically containing about 4.3 at. % boron and about 5 at. % phosphorus. Rapid thermal annealing is then conducted, as at a temperature of about 820° C. for about 120 seconds.
As the distance between sidewall spacers of neighboring gate structures (gap), after depositing the etch stop layer, decreases to below about 0.125 micron, it becomes extremely difficult to fill the gaps with a gap fill oxide, such as a BPSG layer, even after post deposition rapid thermal annealing, without void formation. Such voiding in ILD0 can lead to an open contact and shorting between contacts, thereby causing leakage and low production yields. A solution to this problem attendant upon conventional practices has not been forthcoming. For example, adverting to FIG. 1, a conventional device is schematically illustrated comprising transistors formed on substrate 30, which transistors comprising dual gate structures with an inter-poly (ONO) dielectric therebetween. The transistors typically comprise tunnel oxide 33, floating gate electrode 34, ONO stack inter-poly dielectric 35, and a control gate 36. A layer of metal silicide 37A is formed on an upper surface of the gate electrode stack while a layer of metal silicide 37B is formed on the source/drain regions 31, 32. A dielectric sidewall spacer 38, such as an oxide spacer, is formed on the side surfaces of the gate electrode and conformal silicon nitride etch stop layer 39 is deposited. The narrow gap between the gate structures after depositing the silicon nitride layer is typically no greater than about 0.125 micron. An oxide ILD0 300 is then deposited, such as a BPSG layer, and rapid thermal annealing is conducted. The resulting structure is characterized by voids 301 formed in the narrow gap between the gate stacks.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices, particularly flash memory devices, such as EEPROMs, with improved reliability. There exists a particular need for methodology enabling the fabrication of flash memory devices, such EEPROMs, with no or significantly reduced voids in the ILD0 filling gaps between neighboring transistors.